1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device for use as an object to be evaluated in a method of evaluating whether or not there is contact between adjacent conductor patterns of the semiconductor device.
2. Description of the Background Art
In the manufacturing process of semiconductor devices such as LSI circuits, whether or not there is contact between adjacent interconnect lines has been evaluated without physical contact with the semiconductor devices (as disclosed in Japanese Patent Application Laid-Open No. P62-271444A (1987)).
FIG. 37 is a top plan view of a background art semiconductor device to be evaluated. A plurality of interconnect lines 103a to 103g and a plurality of interconnect lines 104a to 104g are arranged alternately on an upper surface of an insulating film 102. In the arrangement shown in FIG. 37, the interconnect lines 103a to 103g are paired with the interconnect lines 104a to 104g adjacent to the interconnect lines 103a to 103g to constitute a total of seven test patterns 106a to 106g, respectively.
FIG. 38 is a cross-sectional view of the semiconductor device taken along the line A--A of FIG. 37. The insulating film 102 is formed on the entire upper surface of a substrate 101. The interconnect lines 103a and 104a are formed adjacent to each other on the upper surface of the insulating film 102. A contact hole 105a filled with a conductor is formed extending through the insulating film 102 between the upper surface of the insulating film 102 and the upper surface of the substrate 101 under the interconnect line 104a. As a result, the interconnect line 104a is electrically connected through the contact hole 105a to the substrate 101, and the interconnect line 103a is electrically floating. Although there is shown in FIG. 38 only a representative section of the semiconductor device of FIG. 37 in which the interconnect lines 103a and 104a are formed, other sections of the semiconductor device in which the interconnect lines 103b to 103g and the interconnect lines 104b to 104g are formed are similar in construction to the section shown in FIG. 38. Specifically, the interconnect lines 104b to 104g are electrically connected through respective contact holes 105b to 105g filled with a conductor to the substrate 101, and the interconnect lines 103b to 103g are electrically floating.
Referring to FIG. 38, whether or not there is contact between the interconnect lines 103a and 104a may be evaluated by observing the surface of the semiconductor device through an electron microscope such as a SEM (Scanning Electron Microscope). More particularly, charged particles such as an electron beam are directed toward a section of the semiconductor device in which at least the interconnect line 103a is formed, to inject electric charges into the interconnect line 103a. If there is no contact between the interconnect lines 103a and 104a, the electric charges injected in the interconnect line 103a are stored in the interconnect line 103a. Then, the interconnect line 103a is at a predetermined potential depending on the amount of injected electric charges. On the other hand, if there is contact between the interconnect lines 103a and 104a, the electric charges injected in the interconnect line 103a flow through the interconnect line 104a and the contact hole 105a into the substrate 101. That is, the electric charges injected in the interconnect line 103a are not stored in the interconnect line 103a, and the interconnect line 103a is at the same potential as the substrate 101 (e.g., at a ground potential). Thus, the potential at the interconnect line 103a irradiated with the charged particles differs depending on whether or not there is contact between the interconnect lines 103a and 104a. The amount of secondary electrons emitted from the interconnect line 103a differs depending on the level of the potential at the interconnect line 103a.
Therefore, the difference between all of the electrically floating interconnect lines 103a to 103g in the amount of secondary electrons emitted therefrom may be detected as a potential contrast and used to evaluate whether or not there is contact between the interconnect lines 103a to 103g and the interconnect lines 104a to 104g.
In such a background art semiconductor device, the potential at the interconnect line 104a which is one of the single pair of interconnect lines 103a and 104a adjacent to each other is fixed to the potential at the substrate 101, as illustrated in FIG. 38. This requires the formation of the contact hole 105a for establishing an electric connection between the interconnect line 104a and the substrate 101, resulting in an increased number of steps in the manufacturing process of the semiconductor device.
Further, as shown in FIG. 37, the plurality of test patterns 106a to 106g are formed on the upper surface of the insulating film 102 in such a manner that the interconnect lines 103a to 103g and the respectively associated interconnect lines 104a to 104g are in equally spaced apart relationship. Therefore, there has been a need to separately manufacture a plurality of additional semiconductor devices having different interconnect line spacings in order to determine a minimum interconnect line spacing which allows adjacent interconnect lines to be arranged in non-contacting relationship in the photolithographic technique employed for the manufacturing of a semiconductor device.